Central Signal Processor

CentralSignalProcessor_blue

Who are we?

The “Central Signal Processor” (CSP) Consortium is comprised of 13 signatories from 8 countries with more than 10 additional participating organisations. The Consortium includes a rich mixture of engineers, scientists and managers from various academic institutions, industry and government labs spread over 5 continents (see https://www.skatelescope.org/csp/ for more details). As might be expected, it has been a challenge to proceed efficiently with such a diverse and distributed team.

The lead organisation of the Consortium is the National Research Council of Canada (NRC). NRC has contracted MDA Systems Ltd. (a Maxar Company) to assist in leading the Consortium.

What are we designing?

The CSP Element includes design of the hardware and associated firmware/software necessary for the generation of visibilities, searching for new pulsar candidates, and pulsar timing data from the telescope arrays. More background on the CSP can be found in the previous eNews submissions: http://newsletter.skatelescope.org/category/pdf-version-of-enews/

Current Status of Design Activities

Since the last eNews submission in March the CSP Team has completed the submission of all the primary documents for the CSP CDR. This included a revision to the Level 2 requirements and the flowdown to Level 3 requirements. The overall CSP CAPEX and OPEX costing was revised as part of the submission. The CSP CDR is scheduled for September 25-28 at SKAO Headquarters. Progress has also been made on the external ICDs. The Local Monitoring and Control (LMC) Sub-element Team has completed the submission of their CDR data package. The LMC CDR is scheduled for September 24th at SKAO Headquarters.

Key Sub-element Design Development

Local Monitoring and Control (LMC)

The CSP Local Monitoring and Control (LMC) Sub-element is responsible for coordinating all the CSP processing functions according to commands from the Telescope Manager (TM), reporting the overall CSP status based on the reports from the processing sub-elements, and configuring and sequencing the sub-elements. This sub-element is being led by NRC with significant contribution from INAF and assistance from NZA, MDA and NCRA. Significant progress has been achieved on the CDR Deliverables. The INAF team finalised prototyping activities and submitted the prototype report. The Interface Control Documents for the interface with TM and with other CSP sub-elements have been re-structured to comply with the SKA TANGO API design patterns, updated to comply with the latest version of the CBF, PSS and PST designs (as submitted for respective sub-element CDRs), and signed. The CSP LMC requirements have been updated to comply with the CSP Requirement Specification Rev 6 and the corresponding verification requirements have been generated. The design has been finalised and completed resulting in the Detailed Design Document. All LMC CDR deliverables have been provided. The team will now respond to OARs leading up to the CDR September 24.

LOW Correlator and Beamformer (Low.CBF)

The Low.CBF Sub-element Team is made up of members from AUT, ASTRON, and CSIRO. Since the last newsletter in March the Low.CBF Team has been focused on addressing the OARs and comments from the sub-element CDR conducted in March. Revisions to the Level 2 requirements has resulted in changes to the Level 3 requirements. Many of the team members have been very involved in producing the Level 2 CDR artifacts for CSP_Low. The sub-element CDR deliverables will be updated in time for the CSP CDR.

Prototyping has continued with the following progress:

  • Hardware design of Gemini HBM FPGA processing board:
    • Completion of PCB layout and simulations.
    • Completed prototype of blue anodised liquid cooled heatsink and backplane manifolds. Sample has been delivered from ASTRON to CSIRO and is currently being assembled and tested.
    • EMI measurements performed on the Gemini with a large “heater” FPGA design with some EMI “hot” spots on the board to fix.
  • Software prototyping:
    • Design workshop held for the TANGO sub-system architecture and data flows through the complete control system.
    • Commencement of packetised model for FPGA code verification with control inputs from LMC.
  • Firmware Prototyping:
    • Workshops held to assist in writing up and reviewing FPGA Code module descriptions
    • Build framework and board support package functional along with Monitoring and Control
    • Adoption of an AUT developed matrix style correlator that saves a significant amount of FPGA memory.
  • Publications:
    • Two conference papers for the Automatic Register Generation System (ARGS), as well as a paper on the liquid cooled Gemini heatsink.
    • We are proud to say that both primary authors (Mia Baquiran and Paulina Fusiara) are senior female engineers on the Perentie team.

The Perentie Gemini blue anodised liquid cooled heatsink and board (photo credit: Paulina Fusiara)

MID Correlator and Beamformer (Mid.CBF)

The Mid.CBF Sub-element is led by NRC and is based on a Stratix 10 FPGA solution. This is a joint effort with MDA, NZ Alliance and INAF. Since the last newsletter in March the Mid.CBF Team has been focused on addressing the OARs and comments from the sub-element CDR conducted in March. Revisions to the Level 2 requirements has resulted in changes to the Level 3 requirements. The Signal Model document and analysis has been expanded. Many of the team members have been very involved in producing the Level 2 CDR artifacts for CSP_Mid. The sub-element CDR deliverables will be updated in time for the CSP CDR.

Prototyping has continued with the following progress:

  • Firmware design to progress high risk areas of firmware development
    • Design work continues on the top-level correlator FPGA design for the FSP-Part.
  • Monitor and Control Software running on embedded processors
    • U-Boot & Linux OS configuration for HPS on TALON-DX nearly completed.
    • Porting software to Stratix 10 embedded processors well underway.
    • Development and testing of FPGA configuration and partial configuration infrastructure underway.
  • Hardware design of TALON-DX Processing Board
    • 26G and 100GbE tests completed with excellent bit error rates.
    • Fabrication of TALON-DX boards with engineering sample Stratix 10 SX280 FPGAs (with embedded processor) complete and boards are under test.
    • First prototypes received and board bring-up complete.
    • Design considerations allowing TALON-DX Board to support incorporation into DSH Digitizer project are complete.
    • TALON-DX V3 prototype design work to accommodate minor changes for DSH Digitizer nearly complete.
    • Fabrication of TALON-DX boards with production Stratix 10 SX280 FPGAs scheduled for fall 2018 (subject to chip availability).
  • Mechanical/thermal modelling and design work
    • First prototype server LRU boxes received and assembled.
    • Thermal testing of prototype TALON-DX boards underway.

Pulsar Search Engine (PSS)

The PSS Sub-element Team is led by the University of Manchester, University of Oxford and the Max Planck Institute for Radio Astronomy supported by input from INAF Italy, NZ Alliance, ATC Edinburgh, and ASTRON. Since the last newsletter in March the PSS Team has been focused on addressing the OARs and comments from the sub-element CDR conducted in January. Revisions to the Level 2 requirements has resulted in changes to the Level 3 requirements. The sub-element CDR deliverables will be updated in time for the CSP CDR.

Prototyping has continued with the following progress:

  • Significant progress has been made in the setup of the ProtoNIP cluster. It has been successfully populated with a working operating system and associated code. This was a major achievement as the control and roll out across the nodes was a non-trivial exercise, particularly when it needed to be done remotely. So lots of lessons learnt for future deployment.
  • We also undertook extensive power and EMI testing of the prototype node analogs in the UK and are currently writing up the reports on those.

Pulsar Timing Engine (PST)

The PST Sub-element Team consists of members from Swinburne and AUT. Since the last newsletter in March, the PST Team has been focused on addressing the OARs and comments from the sub-element CDR conducted in January. The PST prototype (PT-USE) is currently in operation at MeerKAT and making regular pulsar observations as part of telescope commissioning and early science. PT-USE contributed to the first astrophysical discovery made using MeerKAT, which provided critical radio observations that enabled a multi-wavelength study of a newly revived magnetar (Camilo et al. 2018, Revival of the Magnetar PSR J1622–4950: Observations with MeerKAT, Parkes, XMM-Newton, Swift, Chandra, and NuSTAR, The Astrophysical Journal, Volume 856, Issue 2, article id. 180) [see also https://phys.org/news/2018-04-magnetar-woke-years-silence.html]..

Path to CDR

Overall, the CSP Consortium has made good progress since March. The focus now is to prepare for the CSP CDR meeting in September and respond to OARs as they are provided.


Report provided by the CSP consortium